General description	Features
This core is a multi-master bus arbiter with interrupt handler, based on the AMBA2.0 specification. It is used with a central multiplexer interconnection scheme.	AMBA 2.0 AHB interface Up to 16 masters and slaves Can handle up to 24 interrupt lines per slave Number of interrupts to master depends on master capability. Interrupt to more than one master not supported

Functional description

All masters drive out the address and control signals indicating the transfer they wish to perform and the arbiter determines which master has its address and control signals routed to all of the slaves. A central decoder is also required to control the read data and response signal multiplexer, which selects the appropriate signals from the slave that is involved in the transfer.

(AMBA Specification (Rev 2.0) from ARM Limited.)

Block Diagram