Connector / LED Board - HC-COLEv2
HC-COLEv2 is a connector board for 5 * 20 pin flat ribbon cables. One of the connectors is at the end of the board and not populated, because a hole in the rear panel is required. We deliver together with the child board an Elastomer connector, a plastic strap for the rear panel and all required screws.
Every pin is connected to a LED which shows the logic level. You can activate respectively 20 LED's together with a jumper.
Datasheet |
|
2 Channel 10/100 Mbit Ethernet
The Hpe®_child board HC-ETHv2 offer the developer 2 additional Ethernet connections for the Hpe system. Major component of the interfaces are two National DP83865. These are fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T and 100BASE-TX Ethernet protocols. The DP83865 is an ultra low power version of the DP83861 and DP83891.
Datasheet |
|
2 Channel 10/100/1000 Mbit Ethernet
The Hpe®_childboard HC-ETH2v2 offers two additional Ethernet connections for the Hpe system. Major component of each interface is the Marvell 88E1111. This chip fully features physical layer transceivers with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83865 is an ultra low power version of the DP83861 respectively the DP83891.
Datasheet |
|
IO-Link / HC-IOLZ8v2
The child board was designed to work together with the GE-Research configurable IO-Link IP GERA-IOLZ.
Child board and IP are developed in cooperation with TMG Karlsruhe and support their IO-Link master stack.
Some data of the child Board:
Supports 8 I/O-Link channel
Supports 4 additional direct IO
IO-Link PHY ZIOL2401 from ZMDI
26- pin flat ribbon cable to external connector box
24 V external power supply from ext. connector box
The GERA-IOLZ macro is free configurable for up to 16 IO-Link channels which needs two HC-IOLZ8v2 child boards.
Go to IO-Link Master IP
Go to IO-Link Development Kit
Datasheet
|
|
HC-LVDS8v2
This child board can be used for developing e.g. camera systems with 4 or 6 cameras and LVDS output. 2 cameras per cable if 4 control signals e.g. for SPI are necessary. If only 2 control signals for I2C are required, it’s possible to add 3 cameras per Ethernet cable. We decided to use the Ethernet connector because it’s a cheap and save cabling and not any kind of standard connector for such systems is available.
Datasheet
|
|
HC-SDRv2
The HC-SDRv2 is a standard child board. The module is organized 32Mbit * 64 SDRAM.
The SDRAM module can be used for graphic and video applications where you need a SDRAM directly connected to the internal controller
(independent from the CPU memory bus).
Datasheet
|
|
HC-NAND4v2
The HC-NAND4v2 child board is populated by four NAND- Flash memories. The Flash memories are organized as 1 Giga by 8 bit. Each memory is connected individually to the child board connector, so the user has independent access to the devices.
There are design variants using another NAND- Flash memories from different semiconductor vendors, different memory sizes and different memory organizations (SLC/MLC).
Datasheet |
|
HC-FRMEMv2
The HC-FRMEMv2 child board contains two synchronous Flow Through NtRAMTM with Zero Turnaround between read- and write- cycles. Also there are two 256Mb NOR Flash Memories on the board.
Both memory types share a common address- and a 32- bit data- bus. Memory organization for the RAM’s are 1Mx32 = 4Mbyte, the Flashes have 16Mx32 = 64Mbyte.
Access times for the flashes are 70nSec, the RAM’s have a cycle time of up to 8.5nSec.
Datasheet |
|
