General description	Features
SCARTS is an abbreviation and stands for Scalable Computer Architecture for Real Time Systems. This processor was a development of the Technical University of Vienna.	RISC processor - 122 instructions, all single cycle - Most instructions conditional 4 stage pipeline 16-bit architecture Data path 16 or 32 bit 16 registers (14 general purpose registers) 16 interrupts, 16 traps 4 frame pointer Extensible with hardware accelerators AMBA AHB Bus Interface Harvard Architecture
Developed over years and already used in many student and some industrial projects, this processor is an excellent license free alternative. The SCARTS processor is small and flexible processor, which has been specifically designed for embedded systems with real-time requirements. The deterministic architecture (all instructions execute in one cycle) and the support of conditional instructions significantly simplify the task of WCET analysis.
For SW development is a tool chain, based on the GNU Binutils/GCC/GDB, available. Furthermore there is a port of the Red Hat Newlib, a C standard library for embedded systems. For more information Amazon offers the book: The SCART Hardware/Software Interface See also application note: http://www.ge-research.de/attach/AN-2-005.pdf

Functional description

SPEAR2 represents a RISC architecture which executes instructions in a pipeline. The pipeline has four stages and supports full data forwarding between stages to prevent data hazards. Also control hazards are resolved in hardware. Thus it is not necessary to insert any pipeline stalls.
This feature simplifies the programming and the prediction of worst case execution time. The memory for data and instructions is separated

(Harvard-architecture). The size of the memory is configurable and 1kB of the data memory is reserved for memory mapping of the extension modules.

The instruction set comprises 122 instructions. The width of every instruction is 16 bit and all of them have the same execution time of one cycle.

Most of the instructions are conditional ones. The register file holds 16 registers which are split into 14 general purpose and 2 special function registers which are used to save the return address in case of an interrupt or subroutine call. SPEAR2 supports 32 exceptions. 16 of them are hardware

exceptions (= interrupts) and 16 can be activated by software (= trap).

For building stacks are four stack pointers available. If the processor is idle, it can be put to sleep mode for energy saving.

The processor returns from sleep mode as soon as an interrupt occurs. The most interesting feature is the capability to change the width of the data path. This enables two versions with different performance but same instruction set and interface.

Block Diagram

block diagram